(a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly it pertains to a static induction transistor (SIT) adapted for enhancement mode operation and a semiconductor integrated logic circuit utilizing the static induction transistors, which circuit being suitable for high speed and low power consumption use and high density integration.
(b) Description of the Prior Art
Recently, demands for reduction in size and increase in capacity as well as operation speed in semiconductor logic circuits have been becoming greater, in, for example, the field of electronic computers. Complementary MOS (C-MOS) integrated circuits and merged transistor logic (MTL) circuits have attracted the attention of the industrial circles because these circuits have been considered to satisfy the demands.
In particular, the development of MTL circuits has attracted the attention of the industrial circles widely, because they eliminate at least partially the requirement for the provision of isolating layers for the respective constituent elements, which have been necessary in the conventional logic integrated circuits utilizing combinations of bipolar transistors and which have prevented the realization of a high density integration of circuits; and because the development of MTL circuits has made it possible to realize a high density integration and a relatively low power consumption without sacrificing rapid operation of the bipolar transistor; and also because MTL circuits can be manufactured by relying on the conventional techniques.
Further description of the MTL circuit will be made by referring to the accompanying drawings. FIGS. 1A and 1B show the basic structure of an MTL circuit. FIGS. 1A and 1B differ only in the manner of representing a multi-collector transistor, and these two figures point to substantially the same structure of an MTL circuit. The illustrated MTL structure comprises load transistor 1 having its base electrode grounded and assigned for injecting carriers and an inverter transistor 2 of multi-collectors which is connected to the load transistor 1 so that the control electrode of the output transistor 2 receives the injected carriers. In the conventional MTL structure, both the load transistor and the inverter transistor are formed of bipolar transistors. Furthermore, for the purpose of obtaining a large fan-out (the number of outputs which is greater than one), the inverter transistor is usually formed with a multi-collector transistor. The multi-collector transistor is represented in a manner different from each other in FIGS. 1A and 1B. However, since the switching speed of an MTL is determined by the frequency characteristic of the multi-collector inverter bipolar transistor, a remarkable improvement (e.g. increase in the orders) of the switching speed of MTL cannot be expected. More specifically, the product of time delay .tau. and power dissipation P, .tau..times.P, is used generally as a parameter for the evaluation of the performance of a logic integrated circuit (IC). In the case of a conventional MTL circuit, its .tau..times.P has a value which is of the order of 0.1 to 1 picojoule (pJ) per gate at most. Assuming here that the power disspiation P is 10 .mu.W/gate, the time delay (i.e. the switching speed) will be of the order of 10 to 100 nanoseconds at most. Usually, the time constant .tau. is represented by the product of the resistance and the capacitance, RC. Denoting that supply voltage as V (which is approximately equal to the logic amplitude) and the effective capacitance per gate as C, the delay-power product may be represented as .tau..times.P.apprxeq.RC.times.VI=V.multidot.(RI).multidot.C.apprxeq.V.sup .2 C. If the effective capacitance C is large as in the case of a bipolar transistor, the delay-power product cannot be reduced markedly. In the usual bipolar transistor, the collector is designed to have a large area than that of the emitter. This is because the carriers injected from the emitter diverge in their transfer. In contrast thereto, in a multi-collector transistor, the area of each collector region is exposed on the surface and is samll. Thus, the current amplification factor .beta. becomes small, the fan-out (the number of the outputs of a multi-collector transistor which is controlled of its operation by one input) is 2 to 3 at most. Therefore, noises cannot be suppressed to become extremely small. Furthermore, since the MTL requires the provision of separation layers, of n type in the case of FIGS. 1 and 2, ordinarily for the isolation of the respective gates, these separation layers also hamper the improvement of the integration density. As has been stated above, the currently available integration density of conventional MTL using bipolar transistors is 300 gates/mm.sup.2 at most and the currently available integration density of conventional MTL using MOS transistor is of the order of 100 gates/mm.sup.2.
The static induction transistor (SIT) has been proposed by one of the present inventors, Jun-Ichi Nishizawa, and he has realized a non-saturation type current/voltage characteristic in this SIT. The Nishizawa SIT has proved superior with respect to, for example, high frequency use, current amplification factor, and low noise as compared to bipolar transistors.